1. Field of the Invention
The present invention generally relates to integrated circuits and, in particular, to a method for constructing titanium silicide metal-oxide semiconductor (MOS) integrated circuit electrodes and in interconnections.
2. Description of the Related Art
Field-effect transistors (FET) and other related insulated-gate electronic devices are mainstay components of MOS integrated circuits. A MOSFET generally consists of two closely spaced, doped regions in a substrate--the "source" and the "drain." The region between the two is the "channel." A thin insulation layer is formed directly above the channel. A conductive material "gate" electrode is positioned directly over and completely covering the insulation layer directly above the channel. A voltage applied to the gate affects the electronic properties of the channel region, whereby the FET is turned ON or OFF.
In some devices, such as the electrically erasable programmable read only memory (EEPROM or E2PROM) device, a first gate lies below a superposing insulator layer upon which the gate electrode is constructed; the first gate is known as a "floating gate."
The abbreviation "MOS" has become somewhat of a misnomer because for many applications these gates are formed of a polysilicon material which is doped to render it conductive. However, although such a gate is adequate to create a field in the channel region so as to control the state of the FET, it is not without its operational problems.
One of these problems is that polysilicon has a relatively high sheet resistance and, therefore is not as good a conductor as metal. This, of course, results in slower devices. Hence, manufacturers of integrated circuits have taken to forming composite metal silicide electrodes and interconnections between circuit components. See e.g., U.S. Pat. No. 4,337,476 (Fraser and Murarka).
Hwang, et al., U.S. Pat. No. 4,443,930 teaches a method of cosputtering a target of metal silicide and a target of doped silicon to form a low sheet resistance conductor. However, direct deposit and etching techniques such as this have the disadvantage in that there are difficulties of defining the pattern and creating unsatable transistors. See also, U.S. Pat. No. 4,332,839 (Levinstein, et al.).
Another method of fabricating a metal silicide structure is to form a high resolution pattern prior to depositing a metal silicide layer and then lifting the pattern to leave an electrode/interconnection pattern. See U.S. Pat. No. 4,362,597 (Fraser et al.). Directly deposited polycide (silicide on polysilicon) gates and interconnections have difficulties in defining and controlling the line widths.
One recent solution is proposed by Scovell, et al., U.S. Pat. No. 4,468,308, in which a metallic silicide layer is formed on a substrate by pulse heating deposits to cause interdiffusion.
A major problem of prior techniques occurs in the etching of such a blanket titanium silicide layer to leave only the desired electrodes and interconnections. The silicide will etch at a different rate than adjacent or sandwiched silicon or polysilicon layers. Hence, there exists a tendency to leave silicide which overhangs such layers. When depositing further layers of the structure, such overhangs create flow problems, leaving holes or air bubbles in the structure.
No simple process has been developed which will create a self-aligned, discrete pattern of metal silicide suitable for the geometries involved in the fabrication of integrated circuits.